1. Field of the Invention
The present invention generally relates to digital memory cell circuits for high density integrated circuits and, more particularly, to memory circuits having reduced size with improved soft error immunity.
2. Description of the Prior Art
Modern digital data processors are often limited in program execution speed by the time required for memory access. However, memory access time and the cost of storage varies widely with the storage medium. Therefore, various arrangements have come into widespread use which seek to provide a limited amount of memory in electronic storage, such as static or dynamic random access memories (RAM), which may be accessed very rapidly while larger storage is provided in, for example, magnetic media. Nevertheless, the demand for increased processing speed with reductions in the cost of electronic memory with increased integration density of integrated circuits has led to increased demands for more storage capacity of integrated circuit memories and memory circuits which can be integrated with digital data processing circuits.
In general, static RAM (SRAM) devices provide more rapid access than dynamic RAM (DRAM) since the former are comprised of bistable circuits which have much reduced refresh requirements, if any, and provide reduced response time by sense amplifiers when data is read since an active device rather than a capacitor (which may be partially discharged) provides the signal which is read. Writing speed of SRAMs is also generally faster than DRAMs since there is generally less capacitance on which charge must be developed. However, SRAM memory cells have more elements and thus must generally be larger than DRAM cells even though a capacitor, which is the storage element in DRAM cells, is not necessarily required in SRAM cells.
However, it has been found that the degree to which any given memory cell design can be scaled to smaller sizes without compromising performance is often limited. Additionally, transistor characteristics may be significantly degraded as transistor size and channel length, in particular, is reduced; reducing off resistance and increasing leakage. Similarly, in dynamic memories in which data is stored as charge on a capacitor, operating margins are often severely reduced and refresh rates increased as capacitor size and capacitance are reduced and array size and word and bit line length and capacitance is increased. Perhaps more importantly at the current state of the art, memory cells become increasingly susceptible to soft errors due to ionization and charge injection caused by alpha particles impinging on the chip at or close to the memory cell. It is generally considered that the soft error rate doubles with each new generation of memory device designs. SRAM cells are particularly susceptible to soft errors since charge injection can cause the bistable circuit of the memory cell to switch or flip storage states.
The degree to which a SRAM cell can be physically reduced in size (regardless of any attendant compromise of stability or imposition of operational constraint) is principally limited by the number of transistors required and, to a lesser extent, by the density of connections which must be made in metal layers (particularly the first layer which minimizes connection length and capacitance) formed over the transistors on the chip. Accordingly, SRAM memory cell circuits using fewer transistors have been of interest. In general, SRAM circuits have a minimum of six transistors and are thus referred to as 6T cells: two transistors in each of two cross-coupled inverters to form the bistable element and two additional transistors, sometimes referred to as pass gate transistors, which connect the bistable circuit to bit lines. Several attempts to design a four transistor (4T) SRAM cell have been attempted but have been less than fully successful to date.
In one known approach to a 4T cell design, the pull-up transistors of the bistable circuit are removed from the 6T circuit and specially formed PFET pass gate transistors are used to obtain an increased off-current (as compared to NFETs which are normally used—NFETs normally have greater off-current than PFETS but PFETs can be fabricated to have increased off-currents greater than NFETs, as is done in this particular case) when the bit lines are biased to VDD during standby periods and thus can serve as the pull-up current source. The reduced size made possible by this design is principally due to the reduction of the number of transistors and the use of a so-called direct strap allowing polysilicon and active silicon structures to be shorted together by one contact. However this size reduction and increased integration density is achieved only at the expense of several serious trade-offs.
First, this design is much more susceptible to soft errors than the corresponding 6T design; the resistance of which to soft errors at current minimum feature size regimes such as 0.13 micron and 0.09 micron minimum feature size ground rules is considered marginal although acceptable in some short term and non-critical storage applications such as for display screen memories.
Second, two additional process steps must be employed for the “direct strap” structure and to produce “very leaky” PFET pass gate transistors in order to fully exploit the reduced size possible through reduction of the number of interconnections and transistors.
Third, the requirement for applying VDD to the bit lines during standby periods to provide pull-up essentially precludes constant or consecutive access since the half-selected cells will be disturbed. Half-selected cells refers to the cells along the selected rows and unselected columns or unselected rows and selected columns. Cells along the selected columns and unselected rows will be losing data since the static pull-up leakage current would be missing when the selected bit lines are switched toward ground. Cells along the selected rows and unselected columns will be losing data since the low nodes are pulled up by the pass gate. Since the PFET is made “very leaky” with a special implant process, it will be more conductive than the pulldown NFET and can easily flip the cell. Accordingly, these constraints have prevented this design approach from being applied to memory cells for general applications.
It would be desirable to provide a memory cell which has one or more advantages, such as any of the following: reduced chip area having enhanced immunity to soft errors, which can be formed by processes of reduced complexity and which are free from constraints on continuous or consecutive access.